The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) memory devices and other ICs incorporating embedded memory. More particularly, the present invention relates to a simultaneous function dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) technique of particular applicability to DRAMs, synchronous DRAMs (xe2x80x9cSDRAMxe2x80x9d), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like.
It has long been a goal of memory design to increase the performance of DRAM in order to support higher speed processors. One method of increasing DRAM performance is to increase the xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d data rate across the memory bus. SDRAM access times and burst data rates are constantly improving by manufacturing process xe2x80x9cshrinksxe2x80x9d and improved interconnect technology. Additionally, improved command bus utilization has been achieved by reducing the number of instructions needed to perform certain memory operations. In general, the fewer command cycles which are required for the execution of memory commands results in more bus cycles which are then available for memory data transfers.
To date, several approaches have been used to minimize the number of command cycles needed to access SDRAM devices and embedded arrays. One example is the use of xe2x80x9cburst accessesxe2x80x9d which utilize a single xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d command execution in order to read or write to multiple sequential words. Another technique for reducing the number of command cycles required to access SDRAMs is the use of an xe2x80x9cauto-prechargexe2x80x9d mode of operation. Auto-precharge is a programmable mode wherein a xe2x80x9cprechargexe2x80x9d operation automatically occurs at the end of a predetermined number of burst xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d cycles without requiring the assertion of an external xe2x80x9cprechargexe2x80x9d command. Similarly, the execution of a xe2x80x9crefreshxe2x80x9d command in SDRAMs results in the device automatically precharging at the end of the xe2x80x9crefreshxe2x80x9d operation.
Nevertheless, there are a number of applications, such as in conjunction with graphics processors, where performance could be greatly enhanced if the associated memory supported multiple command executions on a single clock cycle. As an example, a memory architecture that allows for simultaneous xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d operations (used primarily for read-modify-write cycles) may use a xe2x80x9cwritexe2x80x9d address first-in, first-out (xe2x80x9cFIFOxe2x80x9d) register to capture a xe2x80x9creadxe2x80x9d address to be used later as a xe2x80x9cwritexe2x80x9d address. See Hardee, K. et al.; xe2x80x9cA 1.43 GHz Per Data I/O 16 Mb DDR Low-Power Embedded DRAM Macro for a 3D Graphics Enginexe2x80x9d; 2001 IEEE International Solid-State Circuits Conference Digest of Technical Papers; pp 386-387 and ISSCC Visuals Supplement pp 316-317. Further, the concept of capturing the xe2x80x9creadxe2x80x9d address and using it at a later time via a pipeline is described in U.S. Pat. No. 5,996,052 issued Nov. 30, 1999 to Taniguchi et al. for: xe2x80x9cMethod and Circuit for Enabling a Clock-Synchronized Read-Modify-Write Operation on a Memory Arrayxe2x80x9d.
While simultaneous xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d operations have been reported in specialty memories (and certain embedded memories) using posted xe2x80x9cwritexe2x80x9d addresses as mentioned above, simultaneous xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d, xe2x80x9cactivexe2x80x9d and xe2x80x9cprechargexe2x80x9d operations in response to external memory commands have apparently not been previously reported.
In this regard, the technique of the present invention advantageously enables the execution of xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d, xe2x80x9cactivexe2x80x9d and xe2x80x9cprechargexe2x80x9d commands to a memory array on a single clock cycle. The technique disclosed herein is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the present invention provides for the use of separate address fields, including bank addresses, for xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d commands, and separate bank addresses for xe2x80x9cactivexe2x80x9d and xe2x80x9cprechargexe2x80x9d commands with a resultant highly parallel operational functionality.
In accordance with the disclosure of the present invention, simultaneous commands are supported through the use of separate bank addresses. As a consequence, parallel xe2x80x9cactivexe2x80x9d, xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d and xe2x80x9cprechargexe2x80x9d commands can be executed on the same clock (xe2x80x9cCLKxe2x80x9d) cycle with only simultaneous xe2x80x9cactivexe2x80x9d and xe2x80x9cprechargexe2x80x9d commands being unable to be executed to the same bank during any given clock cycle.
In a particular representative embodiment disclosed herein, each xe2x80x9cactivexe2x80x9d, xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d and xe2x80x9cprechargexe2x80x9d command has its own dedicated address field, including bank addresses. In this manner, each command can be simultaneously and independently executed during the same clock cycle resulting in much improved memory control bus utilization through this high level of parallel operation.
Through the use of separate xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d addresses together with separate bank addresses for xe2x80x9cprechargexe2x80x9d operations as well, multiple commands may be captured on one edge (e.g. the rising edge) of the clock signal and performed internally to the memory array in parallel. For example, in a conventional four bank memory the address fields are: BA less than 0,1 greater than  (bank address); RA less than 0:X greater than  (row address) and CA less than 0:X greater than  (column address). By contrast, and in accordance with the technique of the present invention, the following new address fields may be utilized: BAA less than 0,1 greater than  (bank address for xe2x80x9cactivexe2x80x9d or row select); BAR less than 0,1 greater than  (bank address for xe2x80x9creadxe2x80x9d commands); BAW less than 0,1 greater than  (bank address for xe2x80x9cwritexe2x80x9d commands); BAP less than 0,1 greater than  (bank address for xe2x80x9cprechargexe2x80x9d); RA less than 0:X greater than  (row address); CAR less than 0:X greater than  (column address for xe2x80x9creadxe2x80x9d commands) and CAW less than 0:X greater than  (column address for xe2x80x9cwritexe2x80x9d commands).
In this regard, the conventional row address strobe (xe2x80x9c/RASxe2x80x9d); column address strobe (xe2x80x9c/CASxe2x80x9d); write enable (xe2x80x9c/WExe2x80x9d) and chip select (xe2x80x9c/CExe2x80x9d) signals may be then replaced with xe2x80x9creadxe2x80x9d, xe2x80x9cwritexe2x80x9d, xe2x80x9cactivexe2x80x9d and xe2x80x9cprechargexe2x80x9d commands with the input/outputs (xe2x80x9cI/Osxe2x80x9d; xe2x80x9cDATA INxe2x80x9d and xe2x80x9cDATA OUTxe2x80x9d) not being common. Used together with the aforementioned address commands, fully parallel memory operation results. While this internally parallel operation adds some extra address bussing over prior art techniques and results in a small increase in DRAM periphery area, it nevertheless allows for a two, three or four (or more) times increase in memory bandwidth.
Particularly disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks and wherein the memory array receives a clock signal and a number of memory array command signals and is configured for reading data therefrom and writing data thereto. The memory array comprises: a row address input for specifying a row address within the memory array; at least one column address input for specifying a column address within the memory array; a bank address read input for specifying one of the memory banks from which data may be read at the specified row and column address; and a bank address write input for substantially concurrently specifying another one of the memory banks to which data may be written at the specified row and column address.
Also disclosed herein is an integrated circuit device including a memory array comprising a plurality of memory banks. The integrated circuit device comprises: a clock input for sequencing operations of said memory array; a command input for receiving at least read, write, active and precharge commands for the memory array; a row address input for specifying a row address within the memory array; first and second column address inputs for specifying independent column addresses for respectively reading data from and writing data to the memory array; and a plurality of bank address inputs, with each of the bank address inputs corresponding to one of the read, write, active and precharge commands.
Further disclosed herein is a method for accessing data in an integrated circuit device including a memory array comprising a plurality of memory banks. The method comprises the steps of: activating a first of the plurality of memory banks on a first clock cycle and activating a second of the plurality of memory banks while substantially concurrently reading data from the first of said plurality of memory banks on a second clock cycle.